Design and Verification Silicon Manager

Responsibilities

• Lead and manage verification activities for complex SS and/or SoC.
• Develop all aspects of logic verification infrastructure and methodology for complex mobile SoC IP or SS blocks.
• Collaborate with design teams to ensure seamless integration of verification methodology into the design process.
• Optimize and improve verification methodologies to increase efficiency and effectiveness.
• Collaborate with both external and internal CAD teams to develop new verification solutions that can improve the quality and efficiency.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 8 years of experience in Design Verification.
• Experience constructing reusable verification components and environments using UVM, System Verilog or equivalent.
• Experience in Portable Stimulus Standard (PSS), formal or emulation based SimXL methodologies.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering or Computer Science, or a related field.
• Experience in one or more of the following: Operating Systems, Memory Management, Caches Hierarchies, Coherency, Memory Consistency Models, Memory Ordering, DDR/LPDDR, PCIe, or Packet Processors.
• Experience working with software teams to define hardware/software interfacing including control/status registers, security, and error handling.
• Experience with Formal verification techniques, System Verilog Assertions (SVA) and assertion-based verification.
• Experience building verification methodologies that span simulation, emulation and FPGA prototypes.