CPU Design Verification Staff Engineer

Job Area

Engineering Group > Hardware Engineering

General Summary

Qualcomm is looking for strong Design Verification (DV) engineers in Bangalore to verify power management features in high-performance, low-power CPUs.

Roles and Responsibilities

• Verify power management features including Boot, Reset, clock gating, power gating, voltage/frequency management (DVFS/DCVS), limit management, and throttling
• Develop comprehensive test plans in collaboration with CPU design and verification teams
• Use simulation and formal verification methods to execute test plans; write checkers, assertions, and develop stimulus
• Verify power intent using Unified Power Format (UPF) methodologies
• Collaborate with system architects, software, and SoC teams to validate system-level use cases
• Work with emulation teams to run verification on emulators and FPGA platforms
• Debug and triage failures in simulation, emulation, and silicon environments

Minimum Qualifications

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field with 4+ years hardware engineering experience
• OR
• Master's degree with 3+ years experience
• OR
• PhD with 2+ years experience

Additional Requirements:

• 3+ years' experience with power management verification in CPU or SoC environments
• Proficiency in assembly, C, C++ programming and scripting languages
• Experience with Verilog/SystemVerilog
• Strong understanding of CPU architectures and power management features such as clock gating, power gating, UPF, DVFS/DCVS, throttling
• Experience in embedded firmware implementation

Preferred Qualifications

• Deep knowledge of CPU microarchitecture, digital logic design, debug features, and DFT (Design for Testability) architecture
• Experience with advanced verification techniques including formal verification and assertions
• Knowledge of DFT methodologies: JTAG, IEEE1500, MBIST, scan dump, memory dump