ASIC RTL Design -Sr Staff

General Summary:

Qualcomm is seeking a seasoned RTL Design Engineer to join its Display Subsystem team. This team delivers innovative and high-performance display solutions that power Qualcomm's product portfolio including VR/AR, Compute, IoT, and Mobile SoCs. The successful candidate will lead front-end RTL design and implementation of next-generation display subsystems, collaborating with cross-functional teams across geographies to ensure high-quality and power-efficient IP integration.

Required Qualifications:

• Education:
• Bachelor's or Master's degree in Electronics & Telecommunication Engineering, Microelectronics, Computer Science, or related fields.
• Experience:
• 9+ years of hands-on experience in RTL design and SoC hardware development.

Technical Skills & Experience:

• Strong domain knowledge in RTL design, integration, and front-end implementation.
• Proficiency in RTL coding using Verilog, VHDL, and SystemVerilog.
• Hands-on experience in microarchitecture design for cores and ASICs.
• Familiarity with EDA tools and flows including:
• Synthesis (e.g., Synopsys Design Compiler, Cadence Genus)
• Static Timing Analysis (STA)
• Linting, CDC (Clock Domain Crossing), Formal Verification, Low Power Design using UPF (Unified Power Format).
• Scripting skills in Perl, Python, or TCL for automation and flow customization.
• Strong debug capabilities across simulation, emulation, and silicon bring-up.
• Experience working in cross-functional and geographically distributed teams.
• Knowledge of performance and power optimization strategies.

Key Responsibilities:

• Design leadership for front-end development of Display Subsystem IPs.
• Perform complete RTL design cycle: microarchitecture, coding, simulation, synthesis, STA, Lint, CDC, and low-power checks.
• Collaborate with technology and circuit design teams to define and finalize IP specifications.
• Partner with verification and physical design teams to ensure clean handoff and successful implementation.
• Integrate Display IP into larger SoC platforms and support SoC teams during system bring-up.
• Engage with software, test, and system teams to enable and validate low-power features.
• Evaluate and implement new low-power techniques and technologies for power-efficient design.
• Conduct performance analysis at block and chip level to identify bottlenecks and propose optimizations.

Soft Skills:

• Strong communication and collaboration skills across time zones.
• Team player with a proactive approach to issue resolution.
• Ability to work independently as well as mentor junior engineers.

Preferred Skills (Bonus):

• Prior experience with display technologies or subsystems.
• In-depth exposure to display protocols and their integration (e.g., MIPI DSI, eDP).
• Understanding of Qualcomm SoC architectures.