SYSynopsys
ASIC Physical Design, Sr Engineer
Hyderabad ₹3-13 LPA Posted 30 May 2025
FULL TIME
Clock tree synthesis and optimization
Floorplanning and power planning
Routing and physical optimization
Timing closure and formal verification
Job Description
- Floor planning, power planning, placement, and optimization
- Clock tree building and optimization
- Routing and optimization
- Timing constraints closure, synthesis, and formal verification
- Extraction, IR drop analysis, EM analysis, and signal integrity
- Physical verification and flow development for advanced technology nodes
- The Impact You Will Have:Enhance the best practices of the physical design flow
- Contribute to the successful implementation of high-performance digital designs
- Drive innovations in low-power design and high-speed clock distribution
- Ensure the integrity and reliability of complex IC designs
- Support the development of cutting-edge technology that shapes the future
- Collaborate with cross-functional teams to meet customer requirements
- What You ll Need:Solid engineering understanding of IC design concepts
- Strong knowledge of the full design cycle from RTL to GDSII
- Expertise in implementation flows and methodologies for deep sub-micron designs
- Experience in high-performance digital design, CAD, high-speed design, low-power design, and high-speed clock design and distribution
- Proven experience with project tape-outs and timing closure
- Proficiency in software and scripting skills (Perl, Tcl, Python)
- Knowledge of Synopsys tools, flows, and methodologies