ASIC Digital Design, Staff Engineer

• Working on functional verification of high-speed serial link PHY IPs for USBx, PCIex, Ethernet, Display, and HDMI protocol standards.
• Studying IP/design blocks/firmware specifications and building/updating verification plans and test cases.
• Building/updating functional verification environments to execute test plans.
• Implementing checkers, assertions, random test generators, high-level transactional models, and bus functional models (BFMs) as per verification plan needs.
• Performing simulation, random and direct stimulus development, and coverage review.
• Working closely with digital designers for debugging and achieving the desired coverage.

The Impact You Will Have:

• Ensuring the accuracy and functionality of high-speed interface IPs, contributing to the development of cutting-edge technology.
• Enhancing the reliability and performance of Synopsys products through meticulous verification processes.
• Driving innovation in the semiconductor industry by verifying complex digital designs.
• Collaborating with a team of skilled professionals to deliver high-quality IPs that meet industry standards.
• Improving the efficiency of the verification process through automation and advanced verification methodologies.
• Contributing to the overall success of Synopsys by ensuring the delivery of robust and reliable IPs to customers.