ASIC Design Lead, Machine Learning, Silicon

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
• 10 years of experience in RTL design.
• Experience leading a team completing the full development cycle of SoC subsystems (e.g., Neural Processing Units, GPU, DSP, or processors, from conception to production).
• Experience working cross-functionally with Software, Architecture, Design Verification, and SoC integration teams.

Preferred qualifications:

• Master's degree or PhD in Computer Science, Electrical Engineering, or a related field.
• Experience in engineering across architecture, micro-architecture, design verification, implementation, emulation, and silicon bring-up.
• Experience with high performance compute IPs (e.g., GPUs, DSPs, or Neural Processing Units).

Responsibilities

• Manage a team of RTL engineers, plan and lead the design of complex machine learning compute IPs by fully understanding the architecture specification, and interact with software and architecture engineers to identify important design requirements.
• Engage with Verification and Silicon Validation teams to ensure functionality of the design.
• Provide input on synthesis, timing closure, and physical design of digital blocks.
• Participate, guide, and motivate the team for timely execution and exceptional Power Performance Area (PPA) benchmarks for these IPs that will go into a wide range of SoCs.
• Work with SoC Design and other cross-functional implementation teams to make sure the IP design is successfully implemented through the downstream domains all the way to tape-out.