ASIC Design for Testability Engineer, Silicon

Minimum qualifications:

• Bachelor's degree or equivalent practical experience.
• 4 years of experience in DFT/DFD flows and methodologies.
• Experience developing DFT specifications and driving DFT architecture.

Preferred qualifications:

• Experience with User Defined Fault Models (UDFM) generation like Cell-Aware and other fault models like GDD, SDD.
• Experience with STA constraints development and analysis for DFT modes and SDF simulations.
• Experience using EDA tools like Design Compiler, DFT Max, FastScan, TetraMax, Tessent, SpyGlass, Modus, Tessent, TestKompress, VCS, NC-Verilog, and waveform debugging.
• Experience in silicon bring-up, debug, and validation of DFT features on ATE, debugging ATPG patterns, Compressed ATPG patterns, MBIST and JTAG related issues.
• Knowledge of various test standards (such as IEEE 1149.10, 1149.6, 1500, 1687) and test formats (such as BSDL, ICL, PDL, STIL, CTL).

Responsibilities:

• Define DFX specifications and develop flows and methodologies for new technology node implementation.
• Implement/Integrate and verify DFT logic (e.g., memory built-in self test (MBIST), scan chains, DFT compression, TAP controller, BSCN, iJTAG instrumentation, functional BIST, logic BIST, and eFuse logic on test chips).
• Work with the silicon engineering team to create test plans and generate test patterns.
• Participate in post-silicon activity like bring up, diagnostics, and characterization.
• Work with EDA and IP vendors to incorporate state-of-the-art DFT/DFD/DFY flows and methodologies. Provide support to internal teams.