ASIC Design For Testability CAD Engineer, Silicon

Responsibilities

• Work with a team of DFT engineers, RTL and Physical Designer Engineers.
• Work on Subsystem level DFT SCAN, MBIST Architecture with multiple voltage, power domains. 
• Write scripts to automate the DFT flow.
• Develop tests that can be used for Production in the ATE flow.

Minimum qualifications:

• Bachelor's degree in Computer Science, Electronics or Electrical Engineering, or equivalent practical experience.
• 5 years of experience in ASIC design for test including complete silicon life cycle through DFT pattern bring-up on ATE and manufacturing.
• Experience with ATPG, Low Power designs, BIST, JTAG, IJTAG tools and flow.
• Experience with DFT EDA tools (e.g., Tessent).

Preferred qualifications:

• 8 years of experience with DFT Design or CAD.
• Experience with DFT for subsystems with multiple physical partitions.
• Experience with Spyglass-DFT, and DFT Scan constraints, and evaluating STA paths.
• Experience in developing automated workflows using Python and Tcl.
• Experience with workflows related to ATPG, Low Power designs, BIST, JTAG, IJTAG tools and flow.
• Experience with DFT EDA tools like Tessent.