ASIC Design Engineer, RTL, Silicon

Role Responsibilities:

• Define microarchitecture for IPs, subsystems, or SoCs, ensuring quality, schedule compliance, and PPA optimization.
• Collaborate with cross-functional teams (Verification, Design for Test, Physical Design, Software) for design decisions and project tracking.
• Create block-level design documents such as interface protocols, block diagrams, transaction flows, and pipelines.
• Perform RTL coding for SS/SoC integration, function/performance simulation debug, and Lint/CDC/FV/UPF checks.

Job Requirements:

• Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
• 3 years of experience in design, multi-power domains with clocking, and SoCs with silicon.
• Proficiency in Verilog or SystemVerilog language.
• Experience with ASIC design methodologies for front quality checks like Lint, CDC/RDC, Synthesis, DFT ATPG/Memory BIST, and Low Power Estimation.