Analog Layout

1.TSMC 16/12nm,7nm,5nm,3nm and below (other foundries are also fine like Intel, Samsung, GF). Preferably TSMC 7nm/5nm/3nm experience.

2.Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support. Analog blocks like Regulators/Charge pumps/Power Management etc..

3.Responsible for on-time delivery of block-level layouts of acceptable quality. TM should work independently.

4.Expertise in Cadence XL/EXL for Layout execution

5.Verification flows - LVS/DRC/DFM/Antenna check/EMIR experience.

6.Verification checks à Mentor Graphic's Caliber DRC/LVS is a must.

7.BE or MTech in Electronics/VLSI Engineering

8.Good communications skills as we work with cross-functional teams.

9.Share the profiles who have good hands-on experience in recent times on lowers nodes. 

Good to have:

Qualifications:

B.Tech/MTech